Mobility Engineering in Vertical Field Effect Transistors Based on Van der Waals Heterostructures

Abstract

Vertical integration of 2D layered materials to form van der Waals heterostructures (vdWHs) offers new functional electronic and optoelectronic devices. However, the mobility in vertical carrier transport in vdWHs of vertical field-effect transistor (VFET) is not yet investigated in spite of the importance of mobility for the successful application of VFETs in integrated circuits. Here, the mobility in VFET of vdWHs under different drain biases, gate biases, and metal work functions is first investigated and engineered. The traps in WSe₂ are the main source of scattering, which influences the vertical mobility and three distinct transport mechanisms: Ohmic transport, trap-limited transport, and space-charge-limited transport. The vertical mobility in VFET can be improved by suppressing the trap states by raising the Fermi level of WSe₂. This is achieved by increasing the injected carrier density by applying a high drain voltage, or decreasing the Schottky barrier at the graphene/WSe₂ and metal/WSe₂ junctions by applying a gate bias and reducing the metal work function, respectively. Consequently, the mobility in Mn vdWH at +50 V gate voltage is about 76 times higher than the initial mobility of Au vdWH. This work enables further improvements in the VFET for successful application in integrated circuits.

The mobility in vertical carrier transport of vertical field-effect transistors (VFETs) composed of 2D layered materials has not previously been investigated in spite of the importance of the mobility for the successful application of VFETs in integrated circuits. The mobility in VFETs of van der Waals heterostructures under different drain biases, gate biases, and metal work functions is investigated and engineerd.

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